One of the continuing goals of the semiconductor industry is the production of smaller microelectronic devices and denser integrated circuits. As device size shrinks and denser integrated circuits are fabricated, the speed of the devices generally increases, and the power consumption per device generally decreases. Moreover, the number of devices which may be fabricated in an integrated circuit generally increases. Accordingly, much development effort has concentrated on shrinking integrated circuit device dimensions into the submicron range.
The field effect transistor (FET) is an important microelectronic device. As is well known to those having skill in the art, a field effect transistor includes spaced-apart source and drain regions in a semiconductor substrate at a face thereof and a gate on the semiconductor substrate face between the spaced-apart source and drain regions. The field effect transistor also includes a channel in the semiconductor substrate under the gate, between the spaced-apart source and drain regions.
In order to shrink integrated circuit field effect transistor dimensions, much effort has been focused on shrinking the length of the channel between the source and drain regions. However, it has been found that as channel length is reduced to below one micron, to produce "short" channels, departures from conventional long channel behavior may occur. These departures, known as "short channel effects", arise as a result of the two dimensional potential distribution and high electric fields in the channel region.
Short channel effects include a large variation of threshold voltage with processing variations, degradation of subthreshold behavior, decreased saturation current due to punch through, decreased channel mobility, hot carrier injection and other well-known effects. General discussions of short channel effects are contained in publications entitled "Generalized Guide for MOSFET Miniaturization", Brews et al., IEEE Electron Device Letters, Vol. EDL-1, No., January 1980, pp. 2-4; "Constraints on the Application of 0.5 .mu.m MOSFET's to ULSI Systems", Takeda et al., IEEE Transactions on Electron Devices, Vol. ED-32, No. 2, February 1985, pp. 322-327; "Performance and Reliability Design Issues for Deep-Submicrometer MOSFET's", Chung et al., IEEE Transactions on Electron Devices, Vol. 38, No. 3, March 1991, pp. 545-554; and "Threshold Voltage Model for Deep-Submicrometer MOSFET's", Liu et al., IEEE Transactions on Electron Devices, Vol. 40, No. 1, January 1993, pp. 86-95.
In an attempt to reduce or compensate for short channel effects, many short channel FET structures have been developed. Many of these structures provide a channel implant at the substrate surface in order to adjust the threshold of the FET. Other structures include a nonuniformly doped channel by adding extensions of the source and/or drain regions into the channel. Combinations of surface channel implants and source/drain extensions have also been used. See, for example, U.S. Pat. No. 4,636,822 to Codella et al. entitled "GaAs Short Channel Lightly Doped Drain MESFET Structure and Fabrication"; U.S. Pat. No. 5,031,008 to Yoshida entitled "MOSFET Transistor"; U.S. Pat. No. 5,219,777 to Kang entitled "Metal Oxide Semiconductor Field Effect Transistor and Method of Making the Same"; U.S. Pat. No. 5,244,823 to Adan entitled "Process for Fabricating a Semiconductor Device"; and an article entitled "Source-to-Drain Nonuniformly Doped Channel (NUDC) MOSFET Structures for High Current Drivability and Threshold Voltage Controllability" to Okumura et al., IEEE Transactions on Electron Devices, Vol. 39, No. 11, November 1992, pp. 2541-2551. Unfortunately, a surface channel implant decreases the allowed thermal budget of the transistor. Other structural modifications for short channel devices have not effectively reduced or eliminated short channel effects, or produce other undesirable effects. Such short channel devices may also present significant fabrication or yield problems.